1. Field of the Invention
The present invention relates to a semiconductor memory device and most specifically to a semiconductor memory device having the configuration of a cache DRAM.
2. Description of the Background Art
Since the performance such as operation speed of computer systems has recently considerably improved especially in CPUs, a larger band width is in great demand for DRAMs (dynamic RAMs) as well.
As one solution to this problem, "cache DRAMs" have been proposed. In the cache DRAM, a DRAM and an SRAM (static RAM) are formed on one chip to embody, on the one chip, the concept of the cache system.
The cache DRAM is intended to eliminate a speed gap between a CPU and a DRAM by inserting an SRAM and to satisfy the requirements of a high band width in the system by connecting the SRAM and the DRAM with a high band width internal bus.
A conventional semiconductor memory device will be described in the following with reference to FIG. 10. The conventional semiconductor memory device 9000 shown in FIG. 10 has the configuration of a cache DRAM.
The DRAM portion of semiconductor memory device 9000 includes a row selection decoder 105, a column selection decoder 106 and a DRAM array 100. DRAM array 100 includes a plurality of memory cells arranged in rows and columns.
The SRAM portion of semiconductor memory device 9000 includes a row selection decoder 107, a column selection decoder 108 and an SRAM array 102. SRAM array 102 includes a plurality of memory cells arranged in rows and columns.
Conventional semiconductor memory device 9000 further includes a data transfer buffer 901. Data transfer buffer 901 transmits and receives data to and from SRAM array 102 through an SRAM bit line 103. Data transfer buffer 901 also transmits and receives data to and from DRAM array 100 through an internal transfer bus 104.
When such a DRAM portion is to be tested, the following operation is required in conventional semiconductor memory device 9000.
First, data is written to SRAM array 102 (step 1). Then, the data written to SRAM array 102 is transferred to DRAM array 100 (step 2). Then, the data written to DRAM array 100 is transferred to SRAM array 102 (step 3). Thereafter, the data is read from SRAM array 102 (step 4).
However, the number of pins for performing the write/read operations of SRAM array 102 is not so large because of the problems of a system limit and a bus interconnection in the system. Compared with the number of inputs and outputs for the SRAM portion, however, the number of internal transfer buses connecting the SRAM portion and the DRAM portion tends to increase to satisfy the requirements of a high band width.
Accordingly, the process of steps 1 and 4 described above has to be performed a quite larger number of times than the process of steps 2 and 3.
It is assumed as an example that DRAM array 100 has 2 rows and 64 columns with one column consisting of 256 bits, data transfer buffer 901 includes a plurality of buffers which correspond to the bits forming one column, SRAM array 102 has 1 row and 8 columns, with the bit size per column is 256 bits, and there are 32-bit (not shown) inputs/outputs between SRAM array 102 and the outside.
In this case, the following operation is required to write data to the entire row of DRAM array 100. First, the write operation is performed 8 times (32 bits.times.8=256 bits) for SRAM array 102. Then, 256-bit data is transferred from SRAM array 102 to DRAM array 100. This operation is performed 64 times to transfer data of the entire row from the SRAM portion to the DRAM portion.
Further, the following operation is required to read data of the entire row of DRAM array 100. First, 256-bit data is transferred from DRAM array 100 to SRAM array 102. Then, the read operation is performed 8 times for SRAM array 102. This operation is performed 64 times to read all data.
In a series of the write/read operations described above, the DRAM portion is accessed 128 times and the SRAM portion is accessed more than 1024 times.
Thus, in the conventional cache DRAM including an SRAM, access to the SRAM portion is indispensable to test the DRAM portion. Since the SRAM portion is accessed more frequently than the DRAM portion, there is a tendency to increase the test time of the internal operation and complicate the test program. Since the internal buses are increasing to improve the band width, the tendency becomes conspicuous.
Since a large number of pins are required to control the DRAM portion and the SRAM portion in the conventional configuration, an expensive tester has to be used.